View M41T8011_7579812.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

august 2011 doc id 9074 rev 5 1/27 1 m41t80 serial access real-t ime clock with alarm features counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32 khz crystal oscilla tor integrating load capacitance (12.5 pf) providing exceptional oscillator stability and high crystal series resistance operation serial interface supports i 2 c bus (400 khz) 2.0 to 5.5 v clock operating voltage 32 khz square wave on power-up to drive a microcontroller in low-power mode programmable (1 hz to 32 khz) square wave programmable alarm and interrupt function low operating current of 200 a operating temperature of ?40 to 85 c ecopack ? package available 8 1 so8 8-pin soic www.st.com
contents m41t80 2/27 doc id 9074 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 full-time 32 khz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 preferred power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m41t80 list of tables doc id 9074 rev 5 3/27 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. preferred power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. so8 ? 8-lead plastic small outline, 150 m ils body width, package mechanical data . . . . . 22 table 13. carrier tape dimensions for so8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. reel dimensions for 12 mm carrier tape - so8 package (150 mils body width) . . . . . . . . . 24 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures m41t80 4/27 doc id 9074 rev 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 8-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. so8 ? 8-lead plastic small outline, 150 m ils body width, package mechanical drawing. . . 22 figure 14. carrier tape for so8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
m41t80 description doc id 9074 rev 5 5/27 1 description the m41t80 is a low power serial rtc with a built-in 32.768 khz oscillator (external crystal controlled). eight registers (see table 3: clock register map on page 14 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 registers provide status/control of alarm, 32 khz output, and square wave functions. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. functions available to the user include a time-of-day clock/calendar, alarm interrupts, 32 khz output, and programmable square wave output. the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the m41t80 is supplied in an 8-pin soic. figure 1. logic diagram table 1. signal names xi oscillator input xo oscillator output irq /out/sqw interrupt / output driver / square wave (open drain) sda serial data input/output scl serial clock input f 32k 32 khz square wave output (open drain) v cc supply voltage v ss ground scl v cc m41t80 v ss sda f 32k irq/out/sqw xi xo ai07005
description m41t80 6/27 doc id 9074 rev 5 figure 2. 8-pin soic connections 1. open drain output figure 3. block diagram 1. open drain output 2 3 45 6 8 7 1 irq/out/sqw (1) sda scl v ss xo f 32k (1) xi v cc m41t80 ai07006 real time clock calendar rtc w/alarm square wave irq/out/sqw (1) f 32k (1) af sda scl i 2 c interface 32khz oscillator crystal ai07007
m41t80 operation doc id 9074 rev 5 7/27 2 operation the m41t80 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 20 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: tenths/hundredths of a second register 2 nd byte: seconds register 3 rd byte: minutes register 4 th byte: century/hours register 5 th byte: day register 6 th byte: date register 7 th byte: month register 8 th byte: year register 9 th byte: control register 10 th byte: 32ke bit 11 th - 16 th bytes: alarm registers 17 th - 19 th bytes: reserved 20 th byte: square wave register 2.1 2-wire bus characteristics the bus is intended for communication between di fferent ic?s. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
operation m41t80 8/27 doc id 9074 rev 5 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 4. serial bus data transfer sequence ai005 8 7 data clock data line s table data valid s ta rt condition change of data allowed s top condition
m41t80 operation doc id 9074 rev 5 9/27 figure 5. acknowledgement sequence figure 6. bus timing requirements sequence ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb ai005 8 9 s da p t s u: s to t s u: s ta t hd: s ta s r s cl t s u:dat t f t hd:dat t r t high t low t hd: s ta t buf s p
operation m41t80 10/27 doc id 9074 rev 5 2.2 read mode in this mode the master reads the m41t80 slave after setting the slave address ( figure 8: read mode sequence ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be tr ansmitted and the master rece iver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t80 slave transmi tter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h). note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41t80 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 9: alternative read mode sequence ). table 2. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.0 to 5.5 v (except where noted). min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) 2. transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of scl. data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s
m41t80 operation doc id 9074 rev 5 11/27 figure 7. slave address location figure 8. read mode sequence figure 9. alternative read mode sequence ai00602 r/w s lave addre ss s ta rt a 01000 11 m s b l s b ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
operation m41t80 12/27 doc id 9074 rev 5 2.3 write mode in this mode the master transmitter transmits to the m41t80 slave receiver. bus protocol is shown in figure 10: write mode sequence on page 12 . following the start condition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on- chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the m41t80 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see figure 7: slave address location on page 11 and again after it has received the word address and each data byte. figure 10. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
m41t80 clock operation doc id 9074 rev 5 13/27 3 clock operation the m41t80 is driven by a quartz-contro lled oscillator with a nominal frequency of 32,768 hz. the accuracy of the real-time cl ock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the 20-byte register map (see table 3: clock register map on page 14 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/hours register) contain the century enable bit (ceb) and the century bit (cb). se tting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 thr ough d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the contro l register. bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will ca use the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within four seconds (typically one second). the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read. 3.1 clock registers the m41t80 offers 20 internal registers which contain clock, alarm, 32 khz, flag, square wave, and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei ther due to a stop condition or when the pointer increments to any non-clock address (08h-13h). clock and alarm registers store data in bcd. control, 32 khz, and square wave registers store data in binary format.
clock operation m41t80 14/27 doc id 9074 rev 5 table 3. clock register map (1) 1. keys: st = stop bit 0 = must be set to '0' 32ke = enable bit for 32 khz output ceb = enable for century bit cb = century bit out = data bit for out pin afe = alarm flag enable bit rpt1-rpt5 = alarm repeat mode bits af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency select addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10s/100s of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24-hour format) century/ hours 0-1/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out 0 0 0 0 0 0 0 control 09h 32ke 0 0 0 0 0 0 0 32 khz 0ah afe sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh0af0 0 0000 flags 10h00000000reserved 11h00000000reserved 12h00000000reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw
m41t80 clock operation doc id 9074 rev 5 15/27 3.2 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 4: alarm repeat modes shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (and sqwe is '0.'), the alarm condition activates the irq /out/sqw pin. note: if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address poin ter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will incr ement to the flag address, ca using this situation to occur. the irq /out/sqw output is cleared by a read to the flags register as shown in figure 11 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' figure 11. alarm interrupt reset waveform table 4. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year irq/out/sqw active flag 0fh 0eh 10h high-z ai07021
clock operation m41t80 16/27 doc id 9074 rev 5 3.3 full-time 32 khz square wave output the m41t80 offers the user a special 32 khz square wave function which defaults to output on the f 32k pin (pin 3) as long as v cc is valid, and the oscillator is running (st bit = '0'). this function is available within four seconds of initial power-up and can only be disabled by setting the 32ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. note: the f 32k pin is an open drain which requires an external pull-up resistor. 3.4 century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. table 5. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none- 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m41t80 clock operation doc id 9074 rev 5 17/27 3.5 output driver pin when the afe bit and sqwe bit are not set, the irq /out/sqw pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) of address location 08h is a '0,' then the irq /out/sqw pin will be driven low. note: the irq /out/sqw pin is an open drain which requires an external pull-up resistor. 3.6 preferred power-on default when powering the device up from ground (0 v), the following register bits are set to a '0' state: st; afe; and sqwe. the following bits are set to a '1' state: out and 32ke (see table 6: preferred power-on default values on page 17 ). table 6. preferred power-on default values condition st out afe sqwe 32ke power-up (1) 1. if v cc falls to a voltage, 0 v < v cc < 2.0 v, these bits shoul d be rewritten by the user. 0100 1
maximum rating m41t80 18/27 doc id 9074 rev 5 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 7 v t sld (1) 1. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260 c (the time above 255 c must not exceed 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to +6 v i o output current 20 ma p d power dissipation 1 w
m41t80 dc and ac parameters doc id 9074 rev 5 19/27 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 12. ac measurement i/o waveform table 8. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t80 supply voltage (v cc ) 2.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l )100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing ref. voltages 0.3v cc to 0.7v cc table 9. capacitance symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 5 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance 7 pf c out (3) 3. outputs deselected. output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns ai0256 8 0. 8 v cc 0.2v cc 0.7v cc 0. 3 v cc
dc and ac parameters m41t80 20/27 doc id 9074 rev 5 table 10. dc characteristics symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.0 to 5.5 v (except where noted). min typ max unit i li input leakage current 0 v v in v cc 1 a i lo output leakage current 0 v v out v cc 1 a i cc1 supply current switch freq (scl) = 400 khz 3.0 v 30 a 5.5 v 200 a i cc2 (2) 2. at 25 c. supply current (standby) all inputs = v cc ? 0.2 v switch freq (scl) = 0 hz 32ke = 1 or sqwe = 1 3.0 v 1.8 3.0 a 5.5 v 35 a 32ke = 0 and sqwe = 0 3.0 v 1.5 2.4 a 5.5 v 31 a v il input low voltage ?0.3 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.0 ma 0.4 v output low voltage (open drain) (3) 3. for irq /ft/out, rst , and 32 khz pins (open drain) i ol = 10 ma 0.4 v pull-up supply voltage (open drain) irq /out/sqw, f 32k , scl, sda 5.5 v table 11. crystal electrical characteristics sym parameter (1) (2) 1. externally supplied if using the so 8 package. stmicroelectroni cs recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd ) quartz crystal for industr ial temperature operations. 2. load capacitors are integrated within the m41t80. circuit boar d layout considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. min typ max units f o resonant frequency 32.768 khz r s series resistance 60 k c l load capacitance 12.5 pf
m41t80 package mechanical data doc id 9074 rev 5 21/27 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data m41t80 22/27 doc id 9074 rev 5 figure 13. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical drawing 1. drawing is not to scale. table 12. so8 ? 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45 a2 k 0.25 mm l l1 a1 gauge plane
m41t80 package mechanical data doc id 9074 rev 5 23/27 figure 14. carrier tape for so8 package t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 13. carrier tape dimensions for so8 package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty so8 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 6.50 0.10 5.30 0.10 2.20 0.10 8.00 0.10 0.30 0.05 mm 2500
package mechanical data m41t80 24/27 doc id 9074 rev 5 figure 15. reel schematic note: the dimensions given in ta b l e 1 4 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 14. reel dimensions for 12 mm carrier tape - so8 package (150 mils body width) a (max) b (min) c d (min) n (min) g t (max) 330 mm (13-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm
m41t80 part numbering doc id 9074 rev 5 25/27 7 part numbering for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 15. ordering information scheme example: m41t 80 m 6 e device type m41t supply voltage and write protect voltage 80 = v cc = 2.0 to 5.5 v package m = so8 temperature range 6 = ?40 c to 85 c shipping method e = ecopack ? package, tubes (1) 1. shipping in tubes is not recommended for new design. contact local st sales office for availability. f = ecopack ? package, tape & reel
revision history m41t80 26/27 doc id 9074 rev 5 8 revision history table 16. revision history date revision changes oct-2002 1 first issue 15-jun-2004 2 reformatted; add lead-free inform ation; update characteristics ( ta b l e 7 , ta b l e 1 0 , ta b l e 1 5 ) 29-aug-2006 3 changed document to new template; added new features in features on page 1 ; updated package mechanical data in section 6: package mechanical data ; small text changes for entire document, ecopack ? compliant. 15-apr-2010 4 updated ta bl e 7 , 10 , text in section 6 ; reformatted document, minor textual changes. 03-aug-2011 5 added footnote to table 15: ordering information scheme concerning shipping method; added tape an d reel specifications ( figure 14 , 15 , ta b l e 1 3 , 14 ).
m41t80 doc id 9074 rev 5 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M41T8011

	To Download M41T8011 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .